The present invention relates to semiconductor devices and more particularly relates to improvement of an I/O circuit unit including an output transistor for transmitting an output of an internal circuit to the outside and a protection transistor for protecting the internal circuit from an electrostatic discharge (ESD) from the outside.
In a semiconductor integrated circuit, generally, an I/O circuit unit for performing input/output between the outside and an internal circuit is provided in the periphery of a semiconductor chip and the I/O circuit unit includes a plurality of electrode pads. Hereinafter, the structure of a known I/O circuit unit will be described.
FIG. 7 is a circuit diagram of a known I/O circuit unit. In FIG. 7, P101 denotes a p-type MOS transistor, and the source thereof is connected to a power line VDD. N101 denotes an n-type MOS transistor, and the source thereof is connected to a ground line VSS. The respective drains of the MOS transistors P101 and N101 are connected to each other and a node of the MOS transistors P101 and N101 is connected to an electrode pad 102. A series circuit of the p-type MOS transistor P101 and the n-type MOS transistor N101 constitutes an output transistor OT. The output transistor OT is provided plural in number and the plurality of output transistors OT (two output transistors OT in FIG. 7) are connected in parallel with one another. The output transistors OT all have the same structure, and also function as ESD protection transistors.
FIG. 8 is a specific layout of the I/O circuit unit. FIG. 9 is a cross-sectional view taken along the line 1—1 shown in FIG. 8. Note that a gate insulating film and an interlayer insulating film for providing an insulation between wiring layers are not shown in FIG. 8 and FIG. 9.
In FIGS. 8 and 9, 2 denotes a p-type semiconductor substrate, 3 and 4 denote p-type and n-type wells formed on the semiconductor substrate 2, respectively. Two separate NMOS transistors N1 are provided on the p-type well 3, and two separate PMOS transistors P1 are provided on the n-type well 4. The n-type MOS transistors N1 are isolated from the p-type MOS transistors P1 by an isolation region 5. Moreover, in FIGS. 8 and 9, 6 and 7 denote n-type doped regions, which serve as the drain and source of the n-type MOS transistors N1, respectively, and 8 and 9 denote p-type doped regions, which serve as the drain and source of the p-type MOS transistors P1, respectively. Furthermore, VSS denotes a ground line provided in the second wiring layer and VDD denotes a power line provided in the second wiring layer.
The ground line VSS at the ground potential is connected to the n-type doped region 7 serving as the source of the n-type MOS transistor N1 via a via hole 10, an isolated wiring region 11 provided in a first wiring layer, and a via hole 12. In the same manner, the power line VDD at a predetermined potential is connected to the p-type doped region 9 serving as the source of the p-type MOS transistors P1 via a via hole 13, an isolated wiring region 14 provided in the first wiring layer and a via hole 15. Furthermore, 17 denotes an electrode pad provided in the third wiring layer (i.e., an uppermost wiring layer). The electrode pad 17 is located in the periphery of the semiconductor chip and in FIGS. 8 and 9, the electrode pad 17 is provided on the right of the n-type doped region 7 serving as the source of the n-type MOS transistors N1. In addition, 16 denotes a metal line provided on the wiring layer (i.e., the uppermost wiring layer) in which the electrode pad 17 is provided, and connected to the electrode pad 17 at a position close to the right end of the structure shown in FIGS. 8 and 9. Moreover, the metal line 16 is connected to the p-type doped region 8 serving as the drain of the p-type MOS transistors P1 via a stacked via structure including a via hole 18, an isolated wiring region 20 provided in the second wiring layer, a via hole 22, an isolated wiring region 24 provided in the second wiring layer, and a via hole 26, and also connected to the p-type doped region 6 serving as the drain of the n-type MOS transistors N1 via a stacked via structure including a via hole 19, an isolated wiring region 21 provided in the second wiring layer, a via hole 23, an isolated wiring region 25 provided in the first wiring layer, and a via hole 27.
By the way, as the structure of an electrode pad in an I/O circuit unit having the above-described structure, a multi-stepped electrode pad is disclosed in Japanese Laid-Open Patent Publication No. 2000-164620. The electrode pad includes a multi-stepped electrode pad having a relatively wide bonding electrode region 150 and a relatively narrow test electrode region 151, as shown in FIG. 10. The bonding electrode region 150 has a large area enough to reliably allow bonding, and the test electrode region 151 has a small area with which a probe-pin of a test tool is brought into contact. When a test using a probe-pin is conducted, only the test electrode region 151 is used and a probe mark is left only in the test electrode region 151. Thus, bonding to the bonding electrode region 150 can be favorably performed. The electrode pad 152 is provided plural in number. The plurality of electrode pads 152 are arranged in a zigzag manner. Note that in FIG. 10, 153 denotes an I/O circuit unit and 154 denotes a wiring for connecting each of the electrode pads 152 and the I/O circuit unit 153.
In recent years, there has been a strong demand to reduce the size of equipment, for example, portable equipment, in which a semiconductor integrated circuit is provided. With relation to this demand, the size of a semiconductor integrated circuit itself is desired to be reduced.
In response to this demand for reduction in the size of a semiconductor integrated circuit, a POE (pad on element) structure in which an electrode pad is provided over an output transistor which also functions as an ESD protection transistor (and which will be hereinafter referred to as an ESD protection transistor) is considered to be adopted for the purpose of reduction in the size of an I/O circuit unit of a semiconductor integrated circuit. In the POE structure, an electrode pad, a wiring region for connecting the electrode pad to an I/O circuit unit are not needed. Thus, reduction in the size of a semiconductor integrated circuit can be expected.
However, when the above-described multi-stepped structure is used for an electrode pad, the following defect occurs.
Specifically, the multi-stepped electrode pads 152 shown in FIG. 10 is set so that the bonding electrode region 150 has a minimum area for performing a favorable bonding and the test electrode region 151 is set to have a small area in which a probe-pin of a test tool can be favorably in contact with the test electrode region 151. Thus, for example, as shown in FIG. 11, when the respective electrode pads 152 of two adjacent cells A are provided so that one of the electrode pads is arranged reversely to the other, the following problem arises. In FIG. 11, the two adjacent electrode pads 152 are provided so that one of the electrode pads is arranged reversely to the other to satisfy a separation rule between bonding electrode regions 150, and at the same time, test electrode regions 151 are arranged substantially in line so that the probe-pin of the test tool can be brought into contact with the test electrode regions 151 in a simple manner. In this arrangement, in each of the cells A, an I/O circuit unit 155 including an ESD protection transistor is not covered with the electrode pads 152 but only part of the I/O circuit unit 155 is covered with an associated one of the test electrode regions 151. In this case, for example, as shown in FIG. 12A, in each of the cells A, a connection line 160 connected to electrode pads is formed in an uppermost wiring layer located over all of the ESD protection transistors OT so that all of the ESD protection transistors OT are connected to the electrode pads 152. As shown in FIG. 12C illustrating a cross-sectional view taken along the line c—c shown in FIG. 12A, the connection line 160 is connected to the n-type doped region 6 constituting the drain of the n-type MOS transistors N1 via via holes 19, 23 and 27 and isolated wiring regions 21 and 25 and is also connected to the p-type doped region 8 constituting the drain of the p-type MOS transistors P1 via via holes 18, 22 and 26 and isolated wiring region 20 and 24. Assume that the connection line 160 for connecting electrode pads is provided in this manner. As shown in FIG. 12B, when an associated one of the electrode pads 152 is provided over one of the cells A, the electrode pad 152 is not present over an end portion of the connection line 160 connected to electrode pads. Accordingly, as shown in FIG. 12E illustrating a cross-sectional view taken along the line e-e shown in FIG. 12B, the electrode pad 152 is not present over several p-type MOS transistors P1, among MOS transistors (i.e., the p-type MOS transistors P1 of FIG. 12E) constituting the ESD protection transistors, located in an end portion (one p-type MOS transistor P1 in FIG. 12E). Therefore, the connection impedance differs between one of the p-type MOS transistors P1 (particularly, denoted by P0 given in a parenthesis) located at the end portion over which the electrode pad 152 is not present and another one of the p-type MOS transistors P1 located under the electrode pad 152. As a result, since the impedance differs between the ESD protection transistors OT, as described above, a positive or negative voltage of an electrostatic discharge which has come into the electrode pads 152, and ideally, is to be evenly applied to between several ESD protection transistors OT to be released out via each of the ESD protection transistors OT, is not evenly applied thereto and is concentrated. This adversely results in destruction of the ESD protection transistors.
Note that in FIG. 12A, the n-type MOS transistors N101 and the p-type MOS transistors P101 constituting the ESD protection transistors OT are provided so that the n-type MOS transistors N101 and the p-type MOS transistors P101 are arranged in two lines, respectively. Moreover, FIG. 12D is a cross-sectional view taken along the line d—d shown in FIG. 12A.
Moreover, as shown in FIG. 13, when by reducing the width of the cells A to shorten a pitch between the cells A, the cells A are arranged so that no space is provided therebetween in order to dispose a large number of the cells A in the periphery of the semiconductor chip, an arrangement in which the test electrode region 151 of one of the two adjacent ones of the electrode pads 152 and the test electrode region 151 of the other one of the two adjacent electrode pads 152 are provided with no space therebetween is obtained. In this arrangement, an edge portion of the test electrode region 151 of one of the two adjacent electrode pads 152 is interrupted by the wide bonding electrode region 150 of the other of the two adjacent electrode pads 152. As a result, even when it is intended to make the edge portion of the test electrode region 151 extend to reach a further point, the edge portion of the test electrode region 151 can not go beyond the bonding electrode region 150 of the other one of the two adjacent electrode pads 152.
Furthermore, as shown in FIG. 13, even though the pitch between the cells A is shortened, a certain width has to be ensured for the bonding electrode region 150 of each of the electrode pads 152 so that bonding is reliably performed. Therefore, the width of the bonding electrode region 150 is set to be a larger than that of the cells A. Accordingly, the bonding electrode region 150 of each of the electrode pads 152 extends beyond an associated one of the cells A in the inward direction of an adjacent one of the cells A. In that case, the connection line 160 connected to electrode pads is provided in the adjacent one of the cells A. If the bonding electrode region 150 of the electrode pad 152 of the adjacent one of the cells A, which extends in the inward direction of the associated one of the cells A, is present over the connection line 160, the connection line 160 of the cell A and the electrode pad 152 of the adjacent one of the cells A are unintentionally connected to each other.